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Joined: Jul 2000
Posts: 3,718
Hard-core CEG'er
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Hard-core CEG'er
Joined: Jul 2000
Posts: 3,718 |
...and a short lecture is needed on branch prediction and how it is handled in RISC processors as well.
Since you are on a roll here, have at it!
JaTo
e-Tough Guy
Missouri City, TX
99 Contour SVT
#143/2760
00 Corvette Coupe
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Joined: Jan 2004
Posts: 7
Newbie
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Newbie
Joined: Jan 2004
Posts: 7 |
Actually, I have no idea how branch prediction differs between RISC and CISC.
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Joined: May 2000
Posts: 970
Veteran CEG\'er
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Veteran CEG\'er
Joined: May 2000
Posts: 970 |
Last edited by joe; 02/11/04 07:52 PM.
98 GL sport (V6 MTX)
The Durable Duratec? - (DMD, Metal impeller WaterPump, Synth & Stinky in the tranny)
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Joined: Jul 2000
Posts: 3,718
Hard-core CEG'er
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Hard-core CEG'er
Joined: Jul 2000
Posts: 3,718 |
POWER4 has some rather effective algorithms that can keep branch prediction across most workloads between 90-95% accuracy (the highest in the industry on commercial RISC processsors, I think). I belive this has been benchmarked with scientific/technical workloads as well as a number of commercial workloads, though I'll have to check to make sure I'm not fibbing here. I'm positive that sci/tech workloads have seen this high of a rate...
Other RISC techologies in the past were happy to see 60-75% most of the time across either.
In a nutshell, branch prediction tries to "guess" what to do to when a branch instruction is encountered in a pipeline. If it's correct on what to do, it's saved time and cycles in processing instructions; if not, everything has to be flushed out of the pipeline and you start the intruction executions anew (not good).
RISC and CISC branch prediction permutations do differ in how they are implemented; the theory is the same, but how it's handled on a POWER4 processor as compared to some sort of Pentium or Itanium system is an unknown to me. I just know I've been told that they are different and that difference is somewhat considerable.
Intel has been rather murky on how their iteration of branch prediction works; come to think of it, IBM hasn't been much clearer in sessions I've sat in on. Both are usually glossed over in favor of other "flashy" technologies that are going into these chip architectures...
JaTo
e-Tough Guy
Missouri City, TX
99 Contour SVT
#143/2760
00 Corvette Coupe
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Joined: Sep 2000
Posts: 337
CEG\'er
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CEG\'er
Joined: Sep 2000
Posts: 337 |
Originally posted by tdowning:
Processors communicate with RAM in parallel, therefore, for an 8086 chip, 8 bits are transmitted at a time, a 286 is 16-bit, a 386, 486, Pentium, PMMX, PII, PIII, P4, are all 32 bit, as are AMD competiors, the 5x86, K6, K6-2, K6-III, and anything with the "Athlon" moniker.
Minor point. As I recall, the 8086 communicated with RAM 16 bits at a time, vs. the 8088, which did so 8 bits at a time (both used an 8-bit bus for non-memory operations, of course). That, for example, was why IBM chose the 8086 rather than the trusty 8088 for the PS2-30 (which replaced the IBM-XT, which had an 8088). (and for you children, that's Personal System 2, not PlayStation 2).
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Joined: Oct 2000
Posts: 4,149
Hard-core CEG'er
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OP
Hard-core CEG'er
Joined: Oct 2000
Posts: 4,149 |
PS2 got me through undergrad. Hmm, wonder if I still have that around... 
-- 1999 SVT #220 --
In retrospect, it was all downhill from here. RIP, CEG.
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